半導体薄膜歪みゲージ素子

Semiconductor thin film strain gage element

Abstract

PROBLEM TO BE SOLVED: To form at a low temperature a strain gage of a thin film wherein an amorphous silicon carbide phase, a silicon crystallite phase and a silicon carbide crystalite phase are mixed with each other, by making the volumetric ratio of the sum of the silicon and silicon carbide crystallite phases to the whole of the thin film specific. SOLUTION: A crystallization coefficient showing the volumetric ratio of the sum of contained crystal phases to the whole of a thin film is defined as follows. The crystallization coefficient of the thin film containing the crystal phases of silicon crystallite and silicon carbide crystallite is regarded as the sum of both the ratio of the peak intensity corresponding to silicon of the thin film to the crystal peak intensity of silicon powder in X-ray diffraction and the ratio of the peak intensity corresponding to silicon carbide of the thin film to the crystal peak intensity of silicon carbide powder in X-ray diffraction. A thin film 10 containing silicon carbide crystallite is formed by CVD, using as its raw-material gas the mixture of a gas containing Si and C such as silane with a doping gas such as diborane. The strain gage factor of the thin film 10 can reach the one not smaller than 30% under the condition of its formation temperature not higher than 400°C and its crystallization coefficient not smaller than 30%. COPYRIGHT: (C)1997,JPO
(57)【要約】 【課題】 低温形成が可能で、高感度で耐熱安定性に優 れる半導体薄膜歪みゲージ素子の構造を提供する。 【解決手段】 薄膜10の歪みを電気信号に変換して出 力する半導体薄膜歪みゲージ素子であって、薄膜10 が、アモルファス炭化シリコン相と微結晶シリコン相と 微結晶炭化シリコン相とが混在し、微結晶シリコン相の 体積と、微結晶炭化シリコン相の体積の和が、薄膜10 全体の体積の30% 以上となるように成膜した。

Claims

Description

Topics

Download Full PDF Version (Non-Commercial Use)

Patent Citations (0)

    Publication numberPublication dateAssigneeTitle

NO-Patent Citations (0)

    Title

Cited By (0)

    Publication numberPublication dateAssigneeTitle